PCI Bus and VI Bus Mainboard With PCI IDE Controller.jHX
I fiMemory SubsystemDRAM Specifications:See pLigfis 2-9Memory ConfigurationsSee pages Z-io and 2-11 foj chart.Levei Z Cache OptionsSee iuniper section
Technical Summary/1rTermiff^ior Settings5CST devices £Ln? ciijuitit’ted lopethtif iii n 'chain'' by cables. In* temai devices connect
s\PVI-486AP4 User’s ManualRev 1.3 CPU Type SefectiDu; JP17 & 18-19TfiEse Tliree iirmpers sal the CPU type Jf^lB & 19 sef the type and JP17 sij
PVI-486AP4 User’s ManualRev 1.6 CPU Type Selection: JP17 & 18-19These tiinee jumpers set Iti&CPLI tyce. JPlS & l9set tfie type and JPt7 sp
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