華碩 KCMR-D12 系列主板用戶手冊
4-25
Lane Reversal [Disabled]
設置值有:[Disabled] [Enabled]
NB-SB Port Features
NB-SB Link ASPM [L1]
設置值有:[Disabled] [L1]
NP NB-SB VC1 Traffic Support [Disabled]
設置值有:[Disabled] [Enabled]
Complicance Mode [Disabled]
設置值有:[Disabled] [Enabled]
PCIE Slot 2/4 Core Setting; PCIE Slot 5 Core Setting;
PIKE Slot/PCIE Slot 7 Core Setting
Powerdown Unused lanes [Enabled]
設置值有:[Disabled] [Enabled]
Turn Off PLL During L1/L23 [Enabled]
設置值有:[Enabled] [Disabled]
TX Drive Strength [Auto]
設置值有:[Auto] [26mA] [20mA] [22mA] [24mA]
TXCLK Clock Gating in L1 [Enabled]
設置值有:[Enabled] [Disabled]
LCLK Clock Gating in L1 [Enabled]
設置值有:[Enabled] [Disabled]
SB Core Setting
TX Drive Strength [Auto]
設置值有:[Auto] [26mA] [20mA] [22mA] [24mA]
TXCLK Clock Gating in L1 [Enabled]
設置值有:[Disabled] [Enabled]
LCLK Clock Gating in L1 [Enabled]
設置值有:[Disabled] [Enabled]
Hyper Transport 設置(Hyper Transport Configuration)
HT Extended Address [Disabled]
設置值有:[Auto] [Disabled] [Enable]
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