Asus P5CR-L Specifications download pdf (Page 84)

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Chapter 4: BIOS setupChapter 4: BIOS setup

Chapter 4: BIOS setup

4.4.54.4.5

4.4.5

ChipsetChipset

Chipset

The Chipset menu allows you to change the advanced chipset settings.

Select an item then press <Enter> to display the sub-menu.

Advanced Chipset SettingsAdvanced Chipset Settings

Advanced Chipset Settings

Configure DRAM Timing by SPD [Enabled]Configure DRAM Timing by SPD [Enabled]

Configure DRAM Timing by SPD [Enabled]

When this item is enabled, the DRAM timing parameters are set according

to the DRAM SPD (Serial Presence Detect). When disabled, you can

manually set the DRAM timing parameters through the DRAM sub-items.

Configuration options: [Disabled] [Enabled]

The following sub-items appear when this item is Disabled.

DRAM CAS# Latency [5 Clocks]

Controls the latency between the SDRAM read command and the time

the data actually becomes available.

Configuration options: [5 Clocks] [4 Clocks] [3 Clocks]

DRAM RAS# Precharge [4 Clocks]

Controls the idle clocks after issuing a precharge command to the DDR

SDRAM. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks]

[5 Clocks]

DRAM RAS# to CAS# Delay [4 Clocks]

Controls the latency between the DDR SDRAM active command and

the read/write command. Configuration options: [2 Clocks] [3 Clocks]

[4 Clocks] [5 Clocks]

DRAM RAS# Activate to Precharge Delay [15 Clocks]

Configuration options: [1 Clock] ~ [15 Clocks]

DRAM Write Recovery Time [4 Clocks]

Sets the DRAM write recovery time.

Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks]

Enable or disable

DRAM timing.

Advanced Chipset Settings

Configure DRAM Timing by SPD [Enabled]

DRAM ECC Mode [Enabled]

Hyper Path 2 [Auto]

Booting Graphic Priority [Internal VGA]

Onboard LAN Boot ROM [Disabled]

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Asus P5CR-L Specifications Page 84

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