Asus P I-P55TVP4 User Manual download pdf (Page 17)

ASUS P/I-P55T2P4 User's Manual 11

III. INSTALLATION

(Jumpers)

III. INSTALLATION

9. Memory Cacheable Size (JP4)

The default of 64MB uses only the onboard TAG SRAM which allows cacheable

memory up to 64MB. If you install DRAM above 64MB and wish to allow

cacheable memory above 64MB, you need to install a TAG SRAM upgrade or

use a cache module with an extended TAG SRAM (such as 256KB ASUS CM1

Rev 3.0 with 2 TAG SRAM's) but not both and set this jumper to 512MB. See

page 12 for TAG SRAM upgrade and page 14 for cache module information.

WARNING: If there are DRAM cache chips (MCache) either onboard or on

the SIMM cache module instead of pipelined burst SRAM chips, this jumper

must be set to 64MB. 512MB will make the system unstable. Mcache chips can

only allow cacheable memory up to 64MB. See "Map of Motherboard" on page

4 for L2 cache locations. If the cache module that you install already have an

extended tag, do not install another TAG SRAM into the TAG SRAM Upgrade

Socket.

Cacheable Size JP4

64MB (BSRAM/MCache) [1-2] (Default)

512MB (BSRAM Only) [2-3]

Cacheable Size (64MB/512MB)

64MB Cacheable (Default)

Burst SRAM or MCache

512MB Cacheable

Burst SRAM Only

JP4

123

JP4

Compatible Cyrix CPU Identification

The only Cyrix CPU that is supported on this motherboard is

labeled Cyrix 6x86-PR166+ but must be Revision 2.7 or later.

Look on the underside of the CPU for the serial number. The

number should read G8DC6620A or later.

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Asus P I-P55TVP4 User Manual Page 17